[all-commits] [llvm/llvm-project] 70254c: [RISCV] Turn splat shuffles of vector loads into s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 70254ccb69fa82cd953b1609796d239bdcf53923
      https://github.com/llvm/llvm-project/commit/70254ccb69fa82cd953b1609796d239bdcf53923
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

  Log Message:
  -----------
  [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0.

Implementations are allowed to optimize an x0 stride to perform
less memory accesses. This is the case in SiFive cores.

No idea if this is the case in other implementations. We might
need a tuning flag for this.

Reviewed By: frasercrmck, arcbbb

Differential Revision: https://reviews.llvm.org/D100815