[all-commits] [llvm/llvm-project] 528ee1: [AArch64] Block tryCombineToBSL combines for vecto...

[Joe Ellis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 528ee161c9474ce986de13d2e86a970c2074a991
      https://github.com/llvm/llvm-project/commit/528ee161c9474ce986de13d2e86a970c2074a991
  Author: Joe Ellis <joe.ellis at arm.com>
  Date:   2021-04-22 (Thu, 22 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll

  Log Message:
  -----------
  [AArch64] Block tryCombineToBSL combines for vectors wider than NEON

There are no patterns for the AArch64ISD::BSP ISD node for anything
other than NEON vectors at the moment. As a result, if we hit these
combines for vectors wider than a NEON vector (such as what we might get
with fixed length SVE) we will fail to lower.

This patch simply prevents us from attempting the combines if the input
vector type is too wide.

Reviewed By: peterwaller-arm

Differential Revision: https://reviews.llvm.org/D100961