[all-commits] [llvm/llvm-project] f6d8cf: [RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect ca...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6d8cf7798440f303d5a273999e6647cbe795ac6
      https://github.com/llvm/llvm-project/commit/f6d8cf7798440f303d5a273999e6647cbe795ac6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll

  Log Message:
  -----------
  [RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect cases where Hi is sign extended from Lo.

This recognizes the case when Hi is (sra Lo, 31). We can use
SPLAT_VECTOR_I64 rather than splatting the high bits and
combining them in the vector register.