[all-commits] [llvm/llvm-project] a8822c: [RISCV] Temporary in vmsge(u).vx pseudo instructio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a8822caa1baee753273d44b483a636a179791fdc
      https://github.com/llvm/llvm-project/commit/a8822caa1baee753273d44b483a636a179791fdc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/invalid.s

  Log Message:
  -----------
  [RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.

This was checked in some asserts, but not enforced by the
instruction matching.

There's still a second bug that we don't check that vt and vd
are different registers, but that will require custom checking.

Differential Revision: https://reviews.llvm.org/D100928


  Commit: 023b243d1d041185cd1d1291ab6b16ed94ae25fc
      https://github.com/llvm/llvm-project/commit/023b243d1d041185cd1d1291ab6b16ed94ae25fc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Cleanup up the spec version references around fmaxnum/fminnum.

This previously made references to 2.3-draft which was a short
lived version number in 2017. It was replaced by date based
versions leading up to ratification.

This patch uses the latest ratified version number and just says
what the behavior is. Nothing here is in flux.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100878


Compare: https://github.com/llvm/llvm-project/compare/64f47c1e58a1...023b243d1d04