[all-commits] [llvm/llvm-project] 3f02d2: [RISCV] Further fixes for RVV stack offset computa...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f02d269433e1c9b12dee9bf81ea3ec98c212548
      https://github.com/llvm/llvm-project/commit/3f02d269433e1c9b12dee9bf81ea3ec98c212548
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

  Log Message:
  -----------
  [RISCV] Further fixes for RVV stack offset computation

This patch fixes a case missed out by D100574, in which RVV scalable
stack offset computations may require three live registers in the case
where the offset's fixed component is 12 bits or larger and has a
scalable component.

Instead of adding an additional emergency spill slot, this patch further
optimizes the scalable stack offset computation sequences to reduce
register usage.

By emitting the sequence to compute the scalable component before the
fixed component, we can free up one scratch register to be reallocated
by the sequence for the fixed component. Doing this saves one register
and thus one additional emergency spill slot.

Compare:

    $x5 = LUI 1
    $x1 = ADDIW killed $x5, -1896
    $x1 = ADD $x2, killed $x1
    $x5 = PseudoReadVLENB
    $x6 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x6
    $x1 = ADD killed $x1, killed $x5

versus:

    $x5 = PseudoReadVLENB
    $x1 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x1
    $x1 = LUI 1
    $x1 = ADDIW killed $x1, -1896
    $x1 = ADD $x2, killed $x1
    $x1 = ADD killed $x1, killed $x5

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100847