[all-commits] [llvm/llvm-project] ad0fe5: [RISCV][MC] Mask load should not have VMConstraint.

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad0fe5db2fa07595cd96e1c7c422bb6ba75a351f
      https://github.com/llvm/llvm-project/commit/ad0fe5db2fa07595cd96e1c7c422bb6ba75a351f
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/load.s

  Log Message:
  -----------
  [RISCV][MC] Mask load should not have VMConstraint.

Add a test, dest register could be v0.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100825