[all-commits] [llvm/llvm-project] d20a23: [RISCV] Introduce floating point control and state...

[Serge Pavlov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d20a2376d8430a3043edb79bda98f2ef9bbca911
      https://github.com/llvm/llvm-project/commit/d20a2376d8430a3043edb79bda98f2ef9bbca911
  Author: Serge Pavlov <sepavloff at gmail.com>
  Date:   2021-04-21 (Wed, 21 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td

  Log Message:
  -----------
  [RISCV] Introduce floating point control and state registers

New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.

Differential Revision: https://reviews.llvm.org/D99083