[all-commits] [llvm/llvm-project] c91cd4: [AArch64][SVE][InstCombine] Replace last{a, b} intr...

[Joe Ellis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c91cd4f3bb53f6f3b2cbfd6269ebb88eef410246
      https://github.com/llvm/llvm-project/commit/c91cd4f3bb53f6f3b2cbfd6269ebb88eef410246
  Author: Joe Ellis <joe.ellis at arm.com>
  Date:   2021-04-20 (Tue, 20 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-lasta-lastb.ll

  Log Message:
  -----------
  [AArch64][SVE][InstCombine] Replace last{a,b} intrinsics with extracts...

when the predicate used by last{a,b} specifies a known vector length.

For example:
  aarch64_sve_lasta(VL1, D) -> extractelement(D, #1)
  aarch64_sve_lastb(VL1, D) -> extractelement(D, #0)

Co-authored-by: Paul Walker <paul.walker at arm.com>

Differential Revision: https://reviews.llvm.org/D100476