[all-commits] [llvm/llvm-project] 7ed01a: [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ed01a420a2deb609b6b111d968a4dc673c68f19
      https://github.com/llvm/llvm-project/commit/7ed01a420a2deb609b6b111d968a4dc673c68f19
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-19 (Mon, 19 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

  Log Message:
  -----------
  [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.

As noted in the FIXME there's a sort of agreement that the any
extra bits stored will be 0.

The generated code is pretty terrible. I was really hoping we
could use a tail undisturbed trick, but tail undisturbed no
longer applies to masked destinations in the current draft
spec.

Fingers crossed that it isn't common to do this. I doubt IR
from clang or the vectorizer would ever create this kind of store.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100618