[all-commits] [llvm/llvm-project] 91bbb9: [AArch64][GlobalISel] Regbankselect + select @llvm...

[Jessica Paquette via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91bbb914e01715b4b16d49c399b05310aa916cfe
      https://github.com/llvm/llvm-project/commit/91bbb914e01715b4b16d49c399b05310aa916cfe
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2021-04-19 (Mon, 19 Apr 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
    M llvm/lib/CodeGen/GlobalISel/Utils.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-uaddlv.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv

It turns out we actually import a bunch of selection code for intrinsics. The
imported code checks that the register banks on the G_INTRINSIC instruction
are correct. If so, it goes ahead and selects it.

This adds code to AArch64RegisterBankInfo to allow us to correctly determine
register banks on intrinsics which have known register bank constraints.

For now, this only handles @llvm.aarch64.neon.uaddlv. This is necessary for
porting AArch64TargetLowering::LowerCTPOP.

Also add a utility for getting the intrinsic ID from a G_INTRINSIC instruction.
This seems a little nicer than having to know about how intrinsic instructions
are structured.

Differential Revision: https://reviews.llvm.org/D100398