[all-commits] [llvm/llvm-project] 02ef99: [RISCV] Prevent __builtin_riscv_orc_b_64 from bein...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02ef9963e1ad1e6ded539c830861a074b879dc70
      https://github.com/llvm/llvm-project/commit/02ef9963e1ad1e6ded539c830861a074b879dc70
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-08 (Thu, 08 Apr 2021)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsRISCV.def
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/Sema/SemaChecking.cpp
    A clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c

  Log Message:
  -----------
  [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this intrinsic
by just splitting the IR intrinsic since it works on individual bytes.

There will be other intrinsics in the future that would be harder
to support through splitting, for example grev, gorc, and shfl. Those
would require a compare and a select be inserted to check the MSB of
their control input.

This patch adds support for preventing this in the frontend with
a nice diagnostic.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D99984