[all-commits] [llvm/llvm-project] 3dd4aa: [RISCV] When custom iseling masked loads/stores, c...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
      https://github.com/llvm/llvm-project/commit/3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-29 (Mon, 29 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

  Log Message:
  -----------
  [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register.

This matches what we do in our isel patterns. In our internal
testing we've found this is needed to make the fast register
allocator happy at -O0. Otherwise it may assign V0 to an earlier
operand and find itself with no registers left when it reaches
the mask operand. By using V0 explicitly, the fast register allocator
will see it when it checks for phys register usages before it
starts allocating vregs. I'll try to update this with a test case.

Unfortunately, this does appear to prevent some instruction reordering
by the pre-RA scheduler which leads to the increased spills seen in
some tests. I suspect that problem could already occur for other
instructions that already used V0 directly.

There's a lot of repeated code here that could do with some
wrapper functions. Not sure if that should be at the level of the
new code that deals with V0. That would require multiple output
parameters to pass the glue, chain and register back. Maybe it
should be at a higher level over the entire set of push_backs.

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D99367