[all-commits] [llvm/llvm-project] 30080b: [DAGCombiner] Minor compile time improvement to (s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 30080b003e75969155b5baa993b6ffdab602a5ff
      https://github.com/llvm/llvm-project/commit/30080b003e75969155b5baa993b6ffdab602a5ff
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-21 (Sun, 21 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAGCombiner] Minor compile time improvement to (sext_in_reg (sign_extend_vector_inreg x)) optimization.

Don't bother calling ComputeNumSignBits if N00Bits < ExtVTBits. No
matter what answer we get back this will be true:
(N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) < ExtVTBits)

So we might as well save the computation. This makes the code more
consistent with the similar (sext_in_reg (sext x)) handling above.