[all-commits] [llvm/llvm-project] a0f5aa: AMDGPU: Fix allowing immediates for tail call pseudo.

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a0f5aad6d7099e8ecb85f34f7a682b5d1fd088c2
      https://github.com/llvm/llvm-project/commit/a0f5aad6d7099e8ecb85f34f7a682b5d1fd088c2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-21 (Sun, 21 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/MC/AMDGPU/sop1-err.s

  Log Message:
  -----------
  AMDGPU: Fix allowing immediates for tail call pseudo.

The pseudo was using SSrc_b64, so it allowed folding immediates into
the destination operand for a tail call to null. However, this is not
a valid operand for the s_setpc_b64 this will be lowered to. Avoids
printing the operand as an invalid immediate.

Avoids a regression when tail calls are enabled in GlobalISel (somehow
tail calls to null get deleted in the DAG).


  Commit: 20a24af01de2eeb3d1f88fa22cee7201bf13d608
      https://github.com/llvm/llvm-project/commit/20a24af01de2eeb3d1f88fa22cee7201bf13d608
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-21 (Sun, 21 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIRYamlMapping.h
    M llvm/include/llvm/CodeGen/MachineFrameInfo.h
    M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp
    M llvm/test/CodeGen/MIR/Generic/frame-info.mir

  Log Message:
  -----------
  MIR: Fix missing serialization for HasTailCall


Compare: https://github.com/llvm/llvm-project/compare/ffde3acb1b9c...20a24af01de2