[all-commits] [llvm/llvm-project] 64c264: [DAG] Limit (sext_in_reg (zero_extend_vector_inreg...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 64c2641c895ab8d1d71c338294af8252969b7803
      https://github.com/llvm/llvm-project/commit/64c2641c895ab8d1d71c338294af8252969b7803
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-03-21 (Sun, 21 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAG] Limit (sext_in_reg (zero_extend_vector_inreg x)) to exact sign extension

As commented by @craig.topper on rG1ba5c550d418, we can't guarantee that we'll be extending zero bits, just sign bit. So, revert to the old code for zero_extend_vector_inreg cases.