[all-commits] [llvm/llvm-project] 27bc30: [RISCV] Add test case to show a case where (mul (a...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 27bc30c39d62f50fd762a8bcc2dcb0401e7263f7
      https://github.com/llvm/llvm-project/commit/27bc30c39d62f50fd762a8bcc2dcb0401e7263f7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-20 (Sat, 20 Mar 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Add test case to show a case where (mul (and X, 0xffffffff), (and Y, 0xffffffff)) optimization does not improve code.

If the mul add two users, one of which was a sext.w, the mul
would also be selected to a MULW before our pattern runs. This
causes the ANDs to now be used by the already selected MULW and
the mul we still need to select. They are unneeded on the MULW
since MULW only reads the lower bits. So they get selected to
SLLI+SRLI for the MULW use. The use for the
(mul (and X, 0xffffffff), (and Y, 0xffffffff)) manages to reuse
the SLLI.

The end result is increased register pressure and no improvement
to how soon we can start the MULW.