[all-commits] [llvm/llvm-project] 95998b: [Hexagon] Return an i64 for result 0 from LowerREA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95998b898c68206bf0693cc5c1fd17ab9a395cef
      https://github.com/llvm/llvm-project/commit/95998b898c68206bf0693cc5c1fd17ab9a395cef
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-19 (Fri, 19 Mar 2021)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

  Log Message:
  -----------
  [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32.

As far as I can tell, the node coming in has an i64 result so the
return should have the same type. The HexagonISD node used for
this has a type profile that says the result is i64.

Found while trying to add assserts to LegalizeDAG to catch
result type mismatches.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D98962


  Commit: 5d315691c42b57d1858d0f8dc486708bf839cdb3
      https://github.com/llvm/llvm-project/commit/5d315691c42b57d1858d0f8dc486708bf839cdb3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-19 (Fri, 19 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Add missing bitcasts to the results of lowerINSERT_SUBVECTOR and lowerEXTRACT_SUBVECTOR when handling mask vectors.

Found by adding asserts to LegalizeDAG to catch incorrect result
types being returned.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98964


Compare: https://github.com/llvm/llvm-project/compare/fbc1f48daf1b...5d315691c42b