[all-commits] [llvm/llvm-project] aa8d33: [RISCV] Spilling for Zvlsseg registers.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa8d33a6d6346e1ed444a59d0655f4a43ba96875
      https://github.com/llvm/llvm-project/commit/aa8d33a6d6346e1ed444a59d0655f4a43ba96875
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-03-19 (Fri, 19 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    A llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    A llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

  Log Message:
  -----------
  [RISCV] Spilling for Zvlsseg registers.

For Zvlsseg, we create several tuple register classes. When spilling for
these tuple register classes, we need to iterate NF times to load/store
these tuple registers.

Differential Revision: https://reviews.llvm.org/D98629