[all-commits] [llvm/llvm-project] c9861f: [RISCV] Correct the output chain in lowerFixedLeng...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9861f722e375c419a07bcb70c54fe1384cd2999
      https://github.com/llvm/llvm-project/commit/c9861f722e375c419a07bcb70c54fe1384cd2999
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-18 (Thu, 18 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV

We returned the input chain instead of the output chain from the
new load. This bypasses the load in the chain. I haven't found a
good way to test this yet. IR order prevents my initial attempts
at causing reordering.