[all-commits] [llvm/llvm-project] c539be: [Hexagon] Add support for named registers cs0 and cs1

[SidManning via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c539be1dcbcf88530cfaf1728b077feb564b72ec
      https://github.com/llvm/llvm-project/commit/c539be1dcbcf88530cfaf1728b077feb564b72ec
  Author: Sid Manning <sidneym at quicinc.com>
  Date:   2021-03-18 (Thu, 18 Mar 2021)

  Changed paths:
    M clang/lib/Basic/Targets/Hexagon.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/test/CodeGen/Hexagon/namedreg.ll

  Log Message:
  -----------
  [Hexagon] Add support for named registers cs0 and cs1

Allow inline assembly code to referece cs0 and cs1.