[all-commits] [llvm/llvm-project] fca5d6: [RISCV] Fix isel pattern of masked vmslt[u]

[ShihPo Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fca5d63aa8d43a21557874d9bc040e944ab0500d
      https://github.com/llvm/llvm-project/commit/fca5d63aa8d43a21557874d9bc040e944ab0500d
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-03-17 (Wed, 17 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

  Log Message:
  -----------
  [RISCV] Fix isel pattern of masked vmslt[u]

This patch changes the operand order of masked vmslt[u]
from (mask, rs1, scalar, maskedoff, vl)
to (maskedoff, rs1, scalar, mask, vl).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98839