[all-commits] [llvm/llvm-project] 9998b0: [RISCV] Update RVV shift intrinsic tests to use XL...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9998b00c2ecd480c54d3fe806c4011439e41b065
      https://github.com/llvm/llvm-project/commit/9998b00c2ecd480c54d3fe806c4011439e41b065
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2021-03-17 (Wed, 17 Mar 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll

  Log Message:
  -----------
  [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

Fix the unexpected of using op1's element type as shift amount type.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98501