[all-commits] [llvm/llvm-project] 402f2c: [ARM] Use lrdsb for more thumb1 loads.

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 402f2cae7dcaba37ebe33e65bb4e2306ff752bfe
      https://github.com/llvm/llvm-project/commit/402f2cae7dcaba37ebe33e65bb4e2306ff752bfe
  Author: David Green <david.green at arm.com>
  Date:   2021-03-17 (Wed, 17 Mar 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/test/CodeGen/ARM/load.ll
    M llvm/test/CodeGen/ARM/select-imm.ll
    M llvm/test/CodeGen/Thumb/ldr_ext.ll

  Log Message:
  -----------
  [ARM] Use lrdsb for more thumb1 loads.

Given a sextload i16, we can usually generate "ldrsh [rn. rm]". If we
don't naturally have a rn, rm addressing mode, we can either generate
"ldrh [rn, #0]; sxth" or "mov rm, #0; ldrsh [rn. rm]".

We currently generate the first, always creating a sxth. They are both
the same number of instructions, but if we generate the second then the
mov #0 will likely be CSE'd or pulled out of a loop, etc.

This adjusts the ISel patterns to do that, creating a mov instead of a
sxth.

Differential Revision: https://reviews.llvm.org/D98693