[all-commits] [llvm/llvm-project] ff2dd8: [AArch64][SVE] Fold vector ZExt/SExt into gather l...

[Joe Ellis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff2dd8a21251ba0e6d284c9823ff1118a23b59ae
      https://github.com/llvm/llvm-project/commit/ff2dd8a21251ba0e6d284c9823ff1118a23b59ae
  Author: Joe Ellis <joe.ellis at arm.com>
  Date:   2021-03-16 (Tue, 16 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll

  Log Message:
  -----------
  [AArch64][SVE] Fold vector ZExt/SExt into gather loads where possible

This commit folds sxtw'd or uxtw'd offsets into gather loads where
possible with a DAGCombine optimization.

As an example, the following code:

     1	#include <arm_sve.h>
     2
     3	svuint64_t func(svbool_t pred, const int32_t *base, svint64_t offsets) {
     4	  return svld1sw_gather_s64offset_u64(
     5	    pred, base, svextw_s64_x(pred, offsets)
     6	  );
     7	}

would previously lower to the following assembly:

    sxtw	z0.d, p0/m, z0.d
    ld1sw	{ z0.d }, p0/z, [x0, z0.d]
    ret

but now lowers to:

    ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw]
    ret

Differential Revision: https://reviews.llvm.org/D97858