[all-commits] [llvm/llvm-project] 3bffb1: [AMDGPU] Use single cache policy operand

Stanislav Mekhanoshin via All-commits all-commits at lists.llvm.org
Mon Mar 15 13:01:49 PDT 2021 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bffb1cd0ef63858bcc88a6ef39d66c27a872df8
      https://github.com/llvm/llvm-project/commit/3bffb1cd0ef63858bcc88a6ef39d66c27a872df8
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-03-15 (Mon, 15 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SMInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
    M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
    M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
    M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
    M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
    M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
    M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
    M llvm/test/CodeGen/AMDGPU/dead-lane.mir
    M llvm/test/CodeGen/AMDGPU/dead_copy.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
    M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
    M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
    M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
    M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
    M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
    M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/hard-clauses.mir
    M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
    M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
    M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
    M llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
    M llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir
    M llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem-ds.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
    M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
    M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
    M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
    M llvm/test/CodeGen/AMDGPU/memory_clause.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
    M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
    M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
    M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
    M llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
    M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
    M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
    M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
    M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    M llvm/test/CodeGen/AMDGPU/subvector-test.mir
    M llvm/test/CodeGen/AMDGPU/syncscopes.ll
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/wqm.mir
    M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
    M llvm/test/CodeGen/MIR/AMDGPU/load-store-opt-dlc.mir
    M llvm/test/CodeGen/MIR/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
    M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
    M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
    M llvm/test/MC/AMDGPU/atomic-fadd-insts.s
    A llvm/test/MC/AMDGPU/cpol-err.s
    M llvm/test/MC/AMDGPU/flat-gfx10.s
    M llvm/test/MC/AMDGPU/flat-gfx9.s
    M llvm/test/MC/AMDGPU/gfx90a_asm_features.s
    M llvm/test/MC/AMDGPU/gfx90a_err.s
    M llvm/test/MC/AMDGPU/mubuf-gfx10.s

  Log Message:
  -----------
  [AMDGPU] Use single cache policy operand

Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469

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