[all-commits] [llvm/llvm-project] 018e96: [RISCV] Add isel-patterns to optimize (a < 1) into...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 018e96f71ff2d1617aff1ed1abd9c8ad61faf87d
      https://github.com/llvm/llvm-project/commit/018e96f71ff2d1617aff1ed1abd9c8ad61faf87d
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2021-03-15 (Mon, 15 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/branch.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

  Log Message:
  -----------
  [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)

The following code-sequence showed up in a testcase (isolated from
SPEC2017) for if-conversion and vectorization when searching for the
maximum in an array:
        addi    a2, zero, 1
        blt     a1, a2, .LBB0_5
which can be expressed as `bge zero,a1,.LBB0_5`/`blez a1,/LBB0_5`.

More generally, we want to express (a < 1) as (a <= 0).

This adds the required isel-pattern and updates the testcases.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98449