[all-commits] [llvm/llvm-project] d09ae9: [AArch64][SVE] Add unpredicated ld1/st1 patterns f...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d09ae9328f67fd419ab8cea0e73dcdfe8d75f481
      https://github.com/llvm/llvm-project/commit/d09ae9328f67fd419ab8cea0e73dcdfe8d75f481
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-03-15 (Mon, 15 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    A llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    A llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    A llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll

  Log Message:
  -----------
  [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes

Differential Revision: https://reviews.llvm.org/D95677