[all-commits] [llvm/llvm-project] 9c841c: [RISCV] Support extract_vector_elt for fixed and s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c841cb8e8838707b4b005307352d76ed930ee61
      https://github.com/llvm/llvm-project/commit/9c841cb8e8838707b4b005307352d76ed930ee61
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

  Log Message:
  -----------
  [RISCV] Support extract_vector_elt for fixed and scalable masked registers.

This uses a really simple approach of converting to an i8 vector
and extracting. This is probably not the best approach especially
if you know the index is constant.

Other ideas:
-Store to stack temporary using vse1, load as scalar and shift.
-Sort of bitcast the vector to a vector of i8, slide down the
 appropriate 8 bit element, copy to scalar, shift down the
 correct bit within the 8 bits we extracted. Not exactly sure
 how to describe such a bitcast from i1 vector to i8 vector
 within the type system for elements less than 8.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98310