[all-commits] [llvm/llvm-project] e9426d: [ValueTypes][RISCV] Add MVT for v1f16.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e9426dfbaeb2da54e40ca8e02af2eea54637581b
      https://github.com/llvm/llvm-project/commit/e9426dfbaeb2da54e40ca8e02af2eea54637581b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

  Log Message:
  -----------
  [ValueTypes][RISCV] Add MVT for v1f16.

RISCV makes all fixed vector MVTs with size less than or equal
to a command line option legal.

This didn't include v1f16 because it was missing but did include v1f32 and v1f64.

One test is affected where we did test this type, but it is a horizontal
reduction so it is non-sensical. Perhaps we should canonicalize that
away somewhere.

I'm not sure if we should be making v1 types legal, but this will at
least make RISCV consistent across all types.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98365