[all-commits] [llvm/llvm-project] 4f6d79: [AVR] Add register aliases XL, YH, etc

[Ayke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f6d7985d47abd35b657dbc7195c93892726d5f4
      https://github.com/llvm/llvm-project/commit/4f6d7985d47abd35b657dbc7195c93892726d5f4
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2021-03-03 (Wed, 03 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AVR/AVRRegisterInfo.td
    A llvm/test/MC/AVR/registers.s

  Log Message:
  -----------
  [AVR] Add register aliases XL, YH, etc

These aliases are sometimes used in assembly code and make the code more
readable. They are supported by avr-gcc too.

Differential Revision: https://reviews.llvm.org/D96492


  Commit: bbfef8ac952bffb01a7a471a2953cbda77231054
      https://github.com/llvm/llvm-project/commit/bbfef8ac952bffb01a7a471a2953cbda77231054
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2021-03-03 (Wed, 03 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    M llvm/lib/Target/AVR/AVRInstrInfo.td
    M llvm/test/CodeGen/AVR/neg.ll
    M llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir

  Log Message:
  -----------
  [AVR] Fix expansion of NEGW

The previous expansion used SBCI, which is incorrect because the NEGW
pseudo instruction accepts a DREGS operand (2xGPR8) and SBCI only allows
LD8 registers. One solution could be to correct the NEGW pseudo
instruction, but another solution is to use a different instruction
(sbc) that does accept a GPR8 register and therefore allows more freedom
to the register allocator.

The output now matches avr-gcc for the following code:

    int foo(int n) {
        return -n;
    }

I've found this issue using the machine instruction verifier: it was
complaining about the wrong register class in NEGWRd.mir.

Differential Revision: https://reviews.llvm.org/D97131


  Commit: 15f495c0bcb2fcab282582d9a50e234e4103cd1a
      https://github.com/llvm/llvm-project/commit/15f495c0bcb2fcab282582d9a50e234e4103cd1a
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2021-03-03 (Wed, 03 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    M llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
    M llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir

  Log Message:
  -----------
  [AVR] Fix def state of operands

Some instructions (especially mov+pop instructions) were setting the
wrong operands. For example, the pop instruction had the register set as
a source operand while it is a destination operand (the value is loaded
into the register).

I have found these issues using the machine verifier and using manual
code inspection.

Differential Revision: https://reviews.llvm.org/D97159


Compare: https://github.com/llvm/llvm-project/compare/78dcff484120...15f495c0bcb2