[all-commits] [llvm/llvm-project] 183bba: [KnownBits][RISCV] Improve known bits for srem.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 183bbad1d78a4bf445ec4db1ce01673f6a7feb37
      https://github.com/llvm/llvm-project/commit/183bbad1d78a4bf445ec4db1ce01673f6a7feb37
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-21 (Sun, 21 Feb 2021)

  Changed paths:
    M llvm/lib/Support/KnownBits.cpp
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

  Log Message:
  -----------
  [KnownBits][RISCV] Improve known bits for srem.

The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97124