[all-commits] [llvm/llvm-project] 1a6c1a: [SelectionDAG][RISCV] Teach ComputeNumSignBits to ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144
      https://github.com/llvm/llvm-project/commit/1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-21 (Sun, 21 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.

This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.

Reviewed By: luismarques, RKSimon

Differential Revision: https://reviews.llvm.org/D97133