[all-commits] [llvm/llvm-project] 71b68f: [RISCV] Teach our custom vector load/store intrins...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 71b68fe532b3aa8dddf55d1945f26ee3ad3e9867
      https://github.com/llvm/llvm-project/commit/71b68fe532b3aa8dddf55d1945f26ee3ad3e9867
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Teach our custom vector load/store intrinsic isel code to propagate memory operands if we have them.

We don't currently create memory operands for these intrinsics,
but there was a suggestion of using the indexed load/store
intrinsics to implement isel for scalable vector gather/scatter.
That may propagate the memory operand from the gather/scatter
ISD nodes.