[all-commits] [llvm/llvm-project] a32c79: [RISCV] Remove redundant test cases for index segm...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a32c79ce2c355decbf6fd06b492044828c1c957d
      https://github.com/llvm/llvm-project/commit/a32c79ce2c355decbf6fd06b492044828c1c957d
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment load (1/8).

Differential Revision: https://reviews.llvm.org/D97020


  Commit: 320250e4865756545b4187a74faac656120c678b
      https://github.com/llvm/llvm-project/commit/320250e4865756545b4187a74faac656120c678b
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment load (2/8).


  Commit: 8cc0b1cbea7d7ef89a950d709654555ec6949136
      https://github.com/llvm/llvm-project/commit/8cc0b1cbea7d7ef89a950d709654555ec6949136
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment load (3/8).

Differential Revision: https://reviews.llvm.org/D97022


  Commit: 3b4b1c845a4b5e329065f59cb87dce7f528a16fd
      https://github.com/llvm/llvm-project/commit/3b4b1c845a4b5e329065f59cb87dce7f528a16fd
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment load (4/8).


  Commit: de6d640f6d21d78344b6a834f03148963b8a6f5c
      https://github.com/llvm/llvm-project/commit/de6d640f6d21d78344b6a834f03148963b8a6f5c
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment store (5/8).

Differential Revision: https://reviews.llvm.org/D97023


  Commit: b0168a3896eed6ce69886139dc5ae5c983742464
      https://github.com/llvm/llvm-project/commit/b0168a3896eed6ce69886139dc5ae5c983742464
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment store (6/8).

Differential Revision: https://reviews.llvm.org/D97024


  Commit: c2f27da7e7eb514c1e2cb283fe832281fb17819e
      https://github.com/llvm/llvm-project/commit/c2f27da7e7eb514c1e2cb283fe832281fb17819e
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment store (7/8).

Differential Revision: https://reviews.llvm.org/D97025


  Commit: 0ab3558b25d6ba0b4606d3831c9bb1d98c17d113
      https://github.com/llvm/llvm-project/commit/0ab3558b25d6ba0b4606d3831c9bb1d98c17d113
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

  Log Message:
  -----------
  [RISCV] Remove redundant test cases for index segment store (8/8).

Differential Revision: https://reviews.llvm.org/D97026


Compare: https://github.com/llvm/llvm-project/compare/3bf8f162a0a9...0ab3558b25d6