[all-commits] [llvm/llvm-project] b97d8b: [NFC][RISCV] Use concise way to describe load/stor...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2
      https://github.com/llvm/llvm-project/commit/b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

  Log Message:
  -----------
  [NFC][RISCV] Use concise way to describe load/store instructions.

Differential Revision: https://reviews.llvm.org/D96923


  Commit: f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece
      https://github.com/llvm/llvm-project/commit/f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Fix bugs in pseudo instructions for masked segment load.

For masked segment load, the destination register should not overlap
with mask register. It could not be V0.

In the original implementation, there is no segment load/store register
class without V0. In this patch, I added these register classes and
modify `GetVRegNoV0` to get the correct one.

Differential Revision: https://reviews.llvm.org/D96937


Compare: https://github.com/llvm/llvm-project/compare/d248cce44e29...f1efa8abaf8e