[all-commits] [llvm/llvm-project] 766ee1: [Clang][RISCV] Define RISC-V V builtin types

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 766ee1096f0b32616c3e96b7acddc293e56c16ef
      https://github.com/llvm/llvm-project/commit/766ee1096f0b32616c3e96b7acddc293e56c16ef
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M clang/include/clang/AST/ASTContext.h
    M clang/include/clang/AST/Type.h
    M clang/include/clang/AST/TypeProperties.td
    A clang/include/clang/Basic/RISCVVTypes.def
    M clang/include/clang/Basic/TargetInfo.h
    M clang/include/clang/Serialization/ASTBitCodes.h
    M clang/include/clang/module.modulemap
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/AST/ASTImporter.cpp
    M clang/lib/AST/ExprConstant.cpp
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/lib/AST/MicrosoftMangle.cpp
    M clang/lib/AST/NSAPI.cpp
    M clang/lib/AST/PrintfFormatString.cpp
    M clang/lib/AST/Type.cpp
    M clang/lib/AST/TypeLoc.cpp
    M clang/lib/Basic/TargetInfo.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/CodeGen/CGDebugInfo.cpp
    M clang/lib/CodeGen/CodeGenTypes.cpp
    M clang/lib/CodeGen/ItaniumCXXABI.cpp
    M clang/lib/Index/USRGeneration.cpp
    M clang/lib/Sema/Sema.cpp
    M clang/lib/Sema/SemaExpr.cpp
    M clang/lib/Serialization/ASTCommon.cpp
    M clang/lib/Serialization/ASTReader.cpp
    A clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
    A clang/test/Sema/riscv-types.c
    M clang/tools/libclang/CIndex.cpp

  Log Message:
  -----------
  [Clang][RISCV] Define RISC-V V builtin types

Add the types for the RISC-V V extension builtins.

These types will be used by the RISC-V V intrinsics which require
types of the form <vscale x 1 x i64>(LMUL=1 element size=64) or
<vscale x 4 x i32>(LMUL=2 element size=32), etc. The vector_size
attribute does not work for us as it doesn't create a scalable
vector type. We want these types to be opaque and have no operators
defined for them. We want them to be sizeless. This makes them
similar to the ARM SVE builtin types. But we will have quite a bit
more types. This patch adds around 60. Later patches will add
another 230 or so types representing tuples of these types similar
to the x2/x3/x4 types in ARM SVE. But with extra complexity that
these types are combined with the LMUL concept that is unique to
RISCV.

For more background see this RFC
http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html

Authored-by: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>

Differential Revision: https://reviews.llvm.org/D92715