[all-commits] [llvm/llvm-project] df45c1: [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UA...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: df45c1813509fc579c5e0a4f2824923db92c2dbb
      https://github.com/llvm/llvm-project/commit/df45c1813509fc579c5e0a4f2824923db92c2dbb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-02-16 (Tue, 16 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AMDGPU/uaddsat.ll
    M llvm/test/CodeGen/X86/uadd_sat_vec.ll

  Log Message:
  -----------
  [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add

Similar to D96622, we're better off just promoting uaddsat(x,y) -> umin(add(x,y),c) instead of trying to perform a shifted uaddsat.

I initially tried to just use shifted promotion in cases where we didn't have a legal/custom umin - but we don't appear to have any targets that have uaddsat but not umin, so imo we're better off always using the umin and avoid an untested shifted uaddsat code path.

Differential Revision: https://reviews.llvm.org/D96767