[all-commits] [llvm/llvm-project] 23db2d: [AMDGPU] Better selection of base offset when merg...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 23db2d363fd3fe851197fc314f0150976e31be5e
      https://github.com/llvm/llvm-project/commit/23db2d363fd3fe851197fc314f0150976e31be5e
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
    M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
    M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir

  Log Message:
  -----------
  [AMDGPU] Better selection of base offset when merging DS reads/writes

When merging a pair of DS reads or writes needs to materialize the base
offset in a vgpr, choose a value that is aligned to as high a power of
two as possible. This maximises the chance that different pairs can use
the same base offset, in which case the base offset registers can be
commoned up by MachineCSE.

Differential Revision: https://reviews.llvm.org/D96421