[all-commits] [llvm/llvm-project] 574450: [TargetLowering][RISCV][AArch64][PowerPC] Enable B...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5744502a137cbc9f2732e707fde984399b241515
      https://github.com/llvm/llvm-project/commit/5744502a137cbc9f2732e707fde984399b241515
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-11 (Thu, 11 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/BPF/BPFISelLowering.h
    M llvm/test/CodeGen/AArch64/srem-seteq.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
    M llvm/test/CodeGen/AArch64/urem-seteq.ll
    M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll

  Log Message:
  -----------
  [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.

If we wait until the type is legalized, we'll lose information
about the orginal type and need to use larger magic constants.
This gets especially bad on RISCV64 where i64 is the only legal
type.

I've limited this to simple scalar types so it only works for
i8/i16/i32 which are most likely to occur. For more odd types
we might want to do a small promotion to a type where MULH is legal
instead.

Unfortunately, this does prevent some urem/srem+seteq matching since
that still require legal types.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D96210