[all-commits] [llvm/llvm-project] a5b07a: [RISCV] Initial support of LoopVectorizer for RISC...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a5b07a221a5772c0d3733a0bc8ff0b57dd5705de
      https://github.com/llvm/llvm-project/commit/a5b07a221a5772c0d3733a0bc8ff0b57dd5705de
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-02-09 (Tue, 09 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/LoopVectorize/RISCV/lit.local.cfg
    A llvm/test/Transforms/LoopVectorize/RISCV/scalable-vf-hint.ll

  Log Message:
  -----------
  [RISCV] Initial support of LoopVectorizer for RISC-V Vector.

Define an option -riscv-vector-bits-max to specify the maximum vector
bits for vectorizer. Loop vectorizer will use the value to check if it
is safe to use the whole vector registers to vectorize the loop.

It is not the optimum solution for loop vectorizing for scalable vector.
It assumed the whole vector registers will be used to vectorize the code.
If it is possible, we should configure vl to do vectorize instead of
using whole vector registers.

We only consider LMUL = 1 in this patch.

This patch just an initial work for loop vectorizer for RISC-V Vector.

Differential Revision: https://reviews.llvm.org/D95659