[all-commits] [llvm/llvm-project] e046c0: [RISCV] Support scalable-vector integer reduction ...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e046c0c28b108e3799d139e11075a274dcc2ef22
      https://github.com/llvm/llvm-project/commit/e046c0c28b108e3799d139e11075a274dcc2ef22
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-02-05 (Fri, 05 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

  Log Message:
  -----------
  [RISCV] Support scalable-vector integer reduction intrinsics

This patch adds support for the integer reduction intrinsics supported
by RVV. This excludes "mul" which has no corresponding instruction.

The reduction instructions in RVV have slightly complicated type
constraints given they always produce a single "M1" vector register.

They are lowered to custom nodes including the second "scalar" reduction
operand to simplify the patterns and in the hope that they can be useful
for future DAG combines.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95620