[all-commits] [llvm/llvm-project] c3eb2d: [RISCV] Optimize sign-extended EXTRACT_VECTOR_ELT ...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3eb2da6c411ace8e466e329cf6b8de58e711dea
      https://github.com/llvm/llvm-project/commit/c3eb2da6c411ace8e466e329cf6b8de58e711dea
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-02-05 (Fri, 05 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

  Log Message:
  -----------
  [RISCV] Optimize sign-extended EXTRACT_VECTOR_ELT nodes

This patch custom-legalizes all integer EXTRACT_VECTOR_ELT nodes where
SEW < XLEN to VMV_S_X nodes to help the compiler infer sign bits from
the result. This allows us to eliminate redundant sign extensions.

For parity, all integer EXTRACT_VECTOR_ELT nodes are legalized this way
so that we don't need TableGen patterns for some and not others.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95741