[all-commits] [llvm/llvm-project] 25ff30: [RISCV] Split vrgather intrinsics into separate vr...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 25ff302a79f1c27ad03894e74da096ecdbe4176a
      https://github.com/llvm/llvm-project/commit/25ff302a79f1c27ad03894e74da096ecdbe4176a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-04 (Thu, 04 Feb 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll

  Log Message:
  -----------
  [RISCV] Split vrgather intrinsics into separate vrgather.vv and vrgather.vx intrinsics.

The vrgather.vv instruction uses a vector of indices with the same
SEW as operand 0. The vrgather.vx instructions use a scalar index
operand of XLen bits.

By splitting this into 2 intrinsics we are able to use LLVMatchType
in the definition to avoid specifying the type for the index operand
when creating the IR for the intrinsic. For .vv it will match the
operand 0 type. And for .vx it will match the type of the vl operand
we already needed to specify a type for.

I'm considering splitting more intrinsics. This was a somewhat
odd one because the .vx doesn't use the element type, it always
use XLen.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D95979