[all-commits] [llvm/llvm-project] 098dbf: [RISCV] Correct alignment settings for vector regi...

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 098dbf190a5586d02f48b84eb41b93b701cdeb97
      https://github.com/llvm/llvm-project/commit/098dbf190a5586d02f48b84eb41b93b701cdeb97
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Correct alignment settings for vector registers.

According to "9. Vector Memory Alignment Constraints" in V
specification, the alignment of vector memory access is aligned to the
size of the element. In our current implementation, we support ELEN up
to 64. We could assume the alignment of vector registers is 64 under the
assumption.

Differential Revision: https://reviews.llvm.org/D94751