[all-commits] [llvm/llvm-project] 86e604: [RISCV] Add implementation of targetShrinkDemanded...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 86e604c4d68528478333a8901d7c79c09ca16fa8
      https://github.com/llvm/llvm-project/commit/86e604c4d68528478333a8901d7c79c09ca16fa8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-01-15 (Fri, 15 Jan 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.

SimplifyDemandedBits can remove set bits from immediates from instructions
like AND/OR/XOR. This can prevent them from being efficiently
codegened on RISCV.

This adds an initial version that tries to keep or form 12 bit
sign extended immediates for AND operations to enable use of ANDI.
If that doesn't work we'll try to create a 32 bit sign extended immediate
to use LUI+ADDIW.

More optimizations are possible for different size immediates or
different operations. But this is a good starting point that already
has test coverage.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94628