[all-commits] [llvm/llvm-project] 350c05: [NFC][RISCV] Add double type in RISC-V V CodeGen t...
Kai Wang via All-commits
all-commits at lists.llvm.org
Wed Jan 13 07:51:15 PST 2021
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 350c0552c66bf0ca6907b6aa8cede425dedde516
https://github.com/llvm/llvm-project/commit/350c0552c66bf0ca6907b6aa8cede425dedde516
Author: Hsiangkai Wang <kai.wang at sifive.com>
Date: 2021-01-13 (Wed, 13 Jan 2021)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
Log Message:
-----------
[NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32.
Differential Revision: https://reviews.llvm.org/D94584
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