[all-commits] [llvm/llvm-project] ad85e3: [SVE] Add ISel pattern for addvl

[Cullen Rhodes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ad85e3967067154a579f7989ce0e736f8cd56be9
      https://github.com/llvm/llvm-project/commit/ad85e3967067154a579f7989ce0e736f8cd56be9
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-01-13 (Wed, 13 Jan 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/split-vector-insert.ll
    M llvm/test/CodeGen/AArch64/sve-gep.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

  Log Message:
  -----------
  [SVE] Add ISel pattern for addvl

Reviewed By: cameron.mcinally

Differential Revision: https://reviews.llvm.org/D94504