[all-commits] [llvm/llvm-project] c5be0e: [X86] Fix tile register spill issue.

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5be0e0cc0e2fca19a5d130b742ae16c66f99111
      https://github.com/llvm/llvm-project/commit/c5be0e0cc0e2fca19a5d130b742ae16c66f99111
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2021-01-11 (Mon, 11 Jan 2021)

  Changed paths:
    M llvm/lib/CodeGen/InlineSpiller.cpp
    A llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

  Log Message:
  -----------
  [X86] Fix tile register spill issue.

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.

Differential Revision: https://reviews.llvm.org/D93898