[all-commits] [llvm/llvm-project] fdd30f: [RISCV] Define vector widening type-convert intrin...

[Monk Chiang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fdd30faae5b63509f99976f7e52e686a8b39880a
      https://github.com/llvm/llvm-project/commit/fdd30faae5b63509f99976f7e52e686a8b39880a
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2020-12-31 (Thu, 31 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector widening type-convert intrinsic.

Define intrinsics:
  1. vfwcvt.xu.f.v/vfwcvt.x.f.v
  2. vfwcvt.rtz.xu.f.v/vfwcvt.rtz.x.f.v
  3. vfwcvt.f.xu.v/vfwcvt.f.x.v
  4. vfwcvt.f.f.v

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Monk Chiang <monk.chiang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93855


  Commit: 2aed9bc98ab6c33c149b9daefef139626abf70c0
      https://github.com/llvm/llvm-project/commit/2aed9bc98ab6c33c149b9daefef139626abf70c0
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2020-12-31 (Thu, 31 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector narrowing type-convert intrinsic.

Define intrinsics:
  1. vfncvt.xu.f.w/vfncvt.x.f.w
  2. vfncvt.rtz.xu.f.w/vfncvt.rtz.x.f.w
  3. vfncvt.f.xu.w/vfncvt.f.x.w
  4. vfncvt.f.f.w/vfncvt.rod.f.f.w

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Monk Chiang <monk.chiang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93932


  Commit: 1d04cbeb4353ae9d39ca7e8c4de32b65e09bc390
      https://github.com/llvm/llvm-project/commit/1d04cbeb4353ae9d39ca7e8c4de32b65e09bc390
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2020-12-31 (Thu, 31 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vector single-width type-convert intrinsic.

Define intrinsics:
  1. vfcvt.xu.f.v/vfcvt.x.f.v
  2. vfcvt.rtz.xu.f.v/vfcvt.rtz.x.f.v
  3. vfcvt.f.xu.v/vfcvt.f.x.v

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Monk Chiang <monk.chiang at sifive.com>

Differential Revision: https://reviews.llvm.org/D93933


Compare: https://github.com/llvm/llvm-project/compare/ecc38eac7669...1d04cbeb4353