[all-commits] [llvm/llvm-project] 096b02: [RISCV] Add intrinsics for vcompress instruction

[ShihPo Hung via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 096b02ebbff72c403379b28a40f14a8c48e640f8
      https://github.com/llvm/llvm-project/commit/096b02ebbff72c403379b28a40f14a8c48e640f8
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2020-12-29 (Tue, 29 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll

  Log Message:
  -----------
  [RISCV] Add intrinsics for vcompress instruction

This patch defines vcompress intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung at sifive.com>

Differential revision: https://reviews.llvm.org/D93809